(A) Field of the Invention
The present invention relates to a transistor, and more specifically to a Lateral Diffusion Metal-Oxide-Semiconductor (LDMOS) structure related to high-voltage applications.
(B) Description of Related Art
Some of today's hottest products, such as flat panel displays, require high-voltage chips. A commonly used high-voltage device for these applications is the LDMOS transistor or the so-called Drain-Extended MOS. It has the advantages of process compatibility with VLSI process and is easily integrated with other processing.
For high-voltage devices, a specific “on” resistance and breakdown voltage are critical to device performance. A design goal of the LDMOS device is to minimize “on” resistance, while still maintaining a high breakdown voltage. However, these two electrical parameters tend to have conflicting requirements.
FIG. 1 illustrates a high-voltage LDMOS device 1. An N-well 11, a P-well 12 and a P-well 13 are formed in a P-substrate 10. A gate 16 and an oxide layer 161 are formed above the P-substrate 10. Spacers 162 are formed on the sidewalls of the gate 16. A silicide layer 163 may be further formed on the gate 16 as an optional process step. An N+ region 14 is formed in the P-well 12, and another N+ region 15 is formed in the N-well 11. The N+ region 14 serves as a source, whereas the N+ region 15 serves as a drain. The gate 16, the N+ region 14 and the N+ region 15 form an NMOS transistor. Shallow trench isolations (STI) 17 are formed to isolate transistors. In order to withstand high voltages applied to the N+ region 15 (drain), a shallow trench isolation 18 is further formed between the gate 16 and the N+ region 15 to avoid current leakage or cross-talk issues.
The process for manufacturing the shallow trench isolation 18 and the gate structure including the oxide layer 161, the gate 16 and the silicide layer 163 of the LDMOS device 1 is illustrated in FIGS. 2 and 3. In FIG. 2, the shallow trench isolation 18 is formed in a substrate 10, and a sacrificial oxide layer 20 is formed on the substrate 10 to avoid the channel effect that may be caused by subsequent implantations. In FIG. 3, the implantations transform the substrate 10 into the N-well 11, the N+ region 14 and the N+ region 15. Then, the sacrificial oxide layer 20 is removed, and the gate oxide layer 161, the gate 16 and the silicide layer 163 are formed in sequence. Normally, the sacrificial oxide layer 20 is removed by etching with an over-etching percentage of around 20-30% to ensure the sacrificial oxide layer 20 is removed completely. For example, if the thickness of the sacrificial oxide layer 20 is 110 angstroms, the etch time is determined to etch the sacrificial oxide layer 20 to a depth of 133 angstroms.
In consideration of high voltages applied to the LDMOS, the improvement to high breakage voltage is highly demanded but low resistance still needs to be maintained or further improved.